View CY7C1392BV18-278BZXC_2624019.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

18-mbit ddr-ii sio sram 2-word burst architecture cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05623 rev. *c revised june 27, 2006 features ? 18-mbit density (2m x 8, 2m x 9, 1m x 18, 512k x 36) ? 300-mhz clock for high bandwidth ? 2-word burst for reducing address bus frequency ? double data rate (ddr) interfaces (data transferred at 600 mhz) @ 300 mhz ? two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only ? two input clocks for output data (c and c ) to minimize clock-skew an d flight-time mismatches ? echo clocks (cq and cq ) simplify data capture in high-speed systems ? synchronous internally self-timed writes ? 1.8v core power supply with hstl inputs and outputs ? variable drive hstl output buffers ? expanded hstl output voltage (1.4v - v dd ) ? available in 165-ball fbga package (13 x 15 x 1.4 mm) ? offered in lead-free and non lead-free packages ? jtag 1149.1 compatible test access port ? delay lock loop (dll) for accurate data placement configuration cy7c1392bv18 ? 2m x 8 cy7c1992bv18 ? 2m x 9 cy7c1393bv18 ? 1m x18 cy7c1394bv18 ? 512k x 36 functional description the cy7c1392bv18, cy7c1992bv18, cy7c1393bv18, and cy7c1394bv18 are 1.8v synchronous pipelined srams equipped with ddr-ii sio (double data rate separate i/o) architecture. the ddr-ii sio consists of two separate ports to access the memory array. the read port has dedicated data outputs and the write port has dedicated data inputs to completely eliminate the need to ?turn around? the data bus required with common i/o device s. access to each port is accomplished using a common address bus. addresses for read and write are latched on alternate rising edges of the input (k) clock. write data is registered on the rising edges of both k and k . read data is driven on the rising edges of c and c if provided, or on the rising edge of k and k if c/c are not provided. each address location is associated with two 8-bit words in the case of cy7c1392bv18, two 9-bit words in the case of cy7c1992bv18, two 18-bit words in the case of cy7c1393bv18, and two 36-bit words in the case of cy7c1394bv18, that burst sequentially into or out of the device. asynchronous inputs include output impedance matching input (zq). synchronous data ou tputs are tightly matched to the two output echo clocks cq/cq , eliminating the need for separately capturing data from each individual ddr-ii sio sram in the system design. output data clocks (c/c ) enable maximum system clocking and da ta synchronization flexibility. all synchronous inputs pass through input registers controlled by the k/k input clocks. all data outputs pass through output registers controlled by the c or c (or k or k in a single clock domain) input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. selection guide 300 mhz 278 mhz 250 mhz 200 mhz 167 mhz unit maximum operating frequency 300 278 250 200 167 mhz maximum operating current 600 580 550 500 450 ma [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 2 of 27 logic block diagram (cy7c1392bv18) 1m x 8 clk a (19:0) gen. k k control logic address register d [7:0] read add. decode read data reg. ld q [7:0] control logic reg. reg. reg. 8 8 16 write 8 nws 0 v ref write add. decode data reg write data reg memory array 1m x 8 memory array 8 8 20 8 c c nws 1 r/w ld r/w cq cq doff logic block diagram (cy7c1992bv18) 1m x 9 clk a (19:0) gen. k k control logic address register d [8:0] read add. decode read data reg. ld q [8:0] control logic reg. reg. reg. 9 9 18 write 9 bws 0 v ref write add. decode data reg write data reg memory array 1m x 9 memory array 9 9 20 9 c c r/w ld r/w cq cq doff [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 3 of 27 logic block diagram (cy7c1393bv18) 512k x 18 clk a (18:0) gen. k k control logic address register d [17:0] read add. decode read data reg. ld q [17:0] control logic reg. reg. reg. 18 18 36 write 18 bws 0 v ref write add. decode data reg write data reg memory array 512k x 18 memory array 18 18 19 18 c c bws 1 r/w ld r/w cq cq doff logic block diagram (cy7c1394bv18) 128k x 36 clk a (17:0) gen. k k control logic address register d [35:0] read add. decode read data reg. ld q [35:0] control logic reg. reg. reg. 36 36 72 write 36 bws [3:0] v ref write add. decode data reg write data reg memory array 128k x 36 memory array 36 36 18 36 c c r/w ld r/w cq cq doff [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 4 of 27 pin configurations cy7c1392bv18 (2m x 8) 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nws 1 k r/w nc/144m nc nc nc nc nc tdo nc nc d5 nc nc nc tck nc nc a nc/288m k nws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q4 nc v ddq nc nc nc nc q7 a v ddq v ss v ddq v dd v dd q5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d4 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q6 nc d7 d6 v dd a 891011 nc a nc/36m ld cq a nc nc q3 v ss nc nc d3 nc v ss nc q2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d1 v ddq nc q1 nc v ddq v ddq nc v ss nc d0 nc tdi tms v ss a nc a nc d2 nc zq nc q0 nc nc nc nc a cy7c1992bv18 (2m x 9) 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nc k r/w nc/144m nc nc nc nc nc tdo nc nc d5 nc nc nc tck nc nc a nc/288m k bws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q4 nc v ddq nc nc nc nc q7 a v ddq v ss v ddq v dd v dd q5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d4 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q6 nc d7 d6 v dd a 891011 q8 anc/36m ld cq a nc nc q3 v ss nc nc d3 nc v ss nc q2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d1 v ddq nc q1 nc v ddq v ddq nc v ss nc d0 nc tdi tms v ss a nc a nc d2 nc zq nc q0 nc nc d8 nc a 165-ball fbga (13 x 15 x 1.4 mm) pinout [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 5 of 27 pin configurations (continued) cy7c1393bv18 (1m x 18) 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/144m nc/36m bws 1 k r/w nc/288m q9 d9 nc nc nc tdo nc nc d13 nc nc nc tck nc d10 a nc k bws 0 v ss aaa q10 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q11 d12 v ddq d14 q14 d16 q16 q17 a v ddq v ss v ddq v dd v dd q13 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d11 v ss nc v ss q12 nc v ref v ss v dd v ss v ss a v ss c nc q15 nc d17 d15 v dd a 891011 q0 a nc/72m ld cq a nc nc q8 v ss nc q7 d8 nc v ss nc q6 d5 nc nc v ref nc q3 v ddq nc v ddq nc q5 v ddq v ddq v ddq d4 v ddq nc q4 nc v ddq v ddq nc v ss nc d2 nc tdi tms v ss a nc a d7 d6 nc zq d3 q2 d1 q1 d0 nc a 165-ball fbga (13 x 15 x 1.4 mm) pinout cy7c1394bv18 (512k x 36) 234 567 1 a b c d e f g h j k l m n p r a cq q27 d27 d28 d34 doff q33 nc/288m nc/72m bws 2 k r/w bws 1 q18 d18 q30 d31 d33 tdo q28 d29 d22 d32 q34 q31 tck d35 d19 a bws 3 k bws 0 v ss aaa q19 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q20 d21 v ddq d23 q23 d25 q25 q26 a v ddq v ss v ddq v dd v dd q22 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d20 v ss q29 v ss q21 d30 v ref v ss v dd v ss v ss a v ss c q32 q24 q35 d26 d24 v dd a 891011 q0 nc/36m nc/144m ld cq a d17 q17 q8 v ss d16 q7 d8 q16 v ss d15 q6 d5 d9 q14 v ref q11 q3 v ddq q15 v ddq d14 q5 v ddq v ddq v ddq d4 v ddq d12 q4 q12 v ddq v ddq d11 v ss d10 d2 q10 tdi tms v ss a q9 a d7 d6 d13 zq d3 q2 d1 q1 d0 q13 a [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 6 of 27 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals, sampled on the rising edge of k and k clocks during valid write opera- tions . cy7c1392bv18 ? d [7:0] cy7c1992bv18 ? d [8:0] cy7c1393bv18 ? d [17:0] cy7c1394bv18 ? d [35:0] ld input- synchronous synchronous load : this input is brought low when a bus cycle sequence is to be defined. this definition includes address and read/write direction. all transactions operate on a burst of 2 data (one period of bus activity). nws [1:0] input- synchronous nibble write select 0, 1 ? active low (cy7c1392bv18 only) . sampled on the rising edge of the k and k clocks during write operations . used to select which nibble is written into the device during the current portion of the write opera tions. nibbles not written remain unaltered. nws 0 controls d [3:0] and nws 1 controls d [7:4] . all the nibble write selects are sampled on the sa me edge as the data. deselecting a nibble write select will cause the corresponding nibble of data to be ignored and not written into the device. bws [3:0] input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to select which byte is written into the device during the current portion of the write operations. bytes not written remain unaltered. cy7c1992bv18 ? bws 0 controls d [8:0] . cy7c1393bv18 ? bws 0 controls d [8:0] and bws 1 controls d [17:9]. cy7c1394bv18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27] all the byte write selects are sampled on the sa me edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written into the device. a input- synchronous address inputs . sampled on the rising edge of the k clock during active read and write opera- tions. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 2m x 8 (2 arrays each of 1m x 8) for cy7c1392bv18, 2m x 9 (2 arrays each of 1m x 9) for cy7c1992bv18, 1m x 18 (two arrays each of 512k x 18) for cy7c1393bv18 and 1m x 36 (2 arrays each of 128k x 36) for cy7c1394bv18. therefore only 20 address inputs are needed to access the entire memory array of cy7c1392bv18 and cy7c1992bv18, 19 address inputs for cy7c1393bv18, and 18 address inputs for cy7c1394bv18. these inputs are ignored when the appropriate port is deselected. q [x:0] output- synchronous data output signals . these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read o perations or k and k when in single clock mode. when read access is deselected, q [x:0] are automatically tri-stated. cy7c1392bv18 ? q [7:0] cy7c1393bv18 ? q [17:0] cy7c1394bv18 ? q [35:0] r/w input- synchronous synchronous read/write input : when ld is low, this input designates the access type (read when r/w is high, write when r/w is low) for loaded address. r/w must meet the set-up and hold times around edge of k. c input- clock positive input clock for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see app lication example for further details. c input- clock negative input clo ck for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. k input- clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input- clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode. cq echo clock cq is referenced with respect to c . this is a free-running clock and is synchronized to the input clock for output data (c) of the ddr-ii. in the si ngle clock mode, cq is generated with respect to k. the timings for the echo clocks are shown in the ac timing table. [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 7 of 27 functional overview the cy7c1392bv18, cy7c1992bv18, cy7c1393bv18, cy7c1394bv18 are synchronous pipelined burst srams equipped with a ddr-ii separate i/o interface. accesses are initiated on the rising edge of the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the rising edge of the out put clocks, c/c (or k/k when in single clock mode). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the risi ng edge of input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the output clocks, c/c (or k/k when in single clock mode). all synchronous control (r/w , ld , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clock (k). cy7c1393bv18 is described in the following sections. the same basic descriptions apply to cy7c1392bv18, cy7c1992bv18, and cy7c1394bv18. read operations the cy7c1393bv18 is organized internally as two arrays of 1m x 18. accesses are completed in a burst of two sequential 18-bit data words. read operati ons are initiated by asserting r/w high and ld low at the rising edge of the positive input clock (k). the address presented to the address inputs is stored in the read address register. following the next k clock rise the corresponding lowest-order 18-bit word of data is driven onto the q [17:0] using c as the output timing reference. on the subsequent rising edge of c the next 18-bit data word is driven onto the q [17:0] . the requested data will be valid 0.45 ns from the rising edge of the output clock (c or c , or k or k when in single clock mode, for 250-mhz and 200-mhz devices). read accesses can be initiated on every k clock rise. doing so will pipeline the data flow such that data is trans- ferred out of the device on every rising edge of the output clocks, c/c (or k/k when in single clock mode). when read access is deselected, the cy7c1393bv18 will first complete the pending read transactions. synchronous internal circuitry will automat ically tri-state the outputs following the next rising edge of the positive output clock (c). write operations write operations are init iated by asserting r/w low and ld low at the rising edge of the positive input clock (k). on the following k clock rise the data presented to d [17:0] is latched and stored into the lower 18-bit write data register provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ), the information presented to d [17:0] is also stored into the write data register provided bws [1:0] are both asserted active. write accesses can be initiated on every rising edge of input clock (k). doing so pipelines the data flow so that 18 bits of data are written into the device on every rising edge of both input clocks (k and k ). cq echo clock cq is referenced with respect to c . this is a free-running clock and is synchronized to the input clock for output data (c ) of the ddr-ii. in the single clock mode, cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternat ely, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. doff input dll turn off, active low . connecting this pin to ground will turn off the dll inside the device. the timings in the dll turned off operation will be different from those listed in this data sheet. tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc/36m n/a not connected to the die . can be tied to any voltage level. nc/72m n/a not connected to the die . can be tied to any voltage level. nc/144m n/a not connected to the die . can be tied to any voltage level. nc/288m n/a not connected to the die . can be tied to any voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name i/o pin description [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 8 of 27 when write access is deselected, the device will ignore all data inputs after the pending write operations have been completed. byte write operations byte write operations are supported by the cy7c1393bv18. a write operation is initiated as described in the write opera- tions section above. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate byte write select input during the data portion of a write will allow the data being presented to be latched and written into the device. deasserting the byte write select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read/modify/write operations to a byte write operation. single clock mode the cy7c1393bv18 can be used with a single clock that controls both the input and output registers. in this mode the device will recognize only a singl e pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, the user must tie c and c high at power-on. this function is a strap option and not alterable during device operation. the echo clocks are synchronized to input clocks k/k in this mode. ddr operation the cy7c1393bv18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double ddr mode of operation. if a read occurs after a write cycle, address and data for the write are stored in registers. the write information must be stored because the sram can not perform the last word write to the array without conflicting with the read. the data stays in this register until the next write cycle occurs. on the first write cycle after the read(s), the stored data from the earlier write will be written into the sram array. this is called a posted write. depth expansion depth expansion require s replicating the ld control signal for each bank. all other control signals can be common between banks as appropriate. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the va lue of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq = 1.5v. the output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on th e ddr-ii to simplify data capture on high-speed system s. two echo clocks are generated by the ddr-ii. cq is referenced with respect to c and cq is referenced with respect to c . these are free-running clocks and are syn chronized to t he output clock of the separate i/o ddr. in the single clock mode, cq is generated with respect to k and cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. dll these chips utilize a delay lock loop (dll) that is designed to function between 80 mhz and the specified maximum clock frequency. during power-up, when the doff is tied high, the dll gets locked after 1024 cycles of stable clock. the dll can also be reset by slowing or stopping the input clock k and k for a minimum of 30 ns. however, it is not necessary for the dll to be specifically reset in order to lock the dll to the desired frequency. the dll will automatically lock 1024 clock cycles after a stable clock is presented.the dll may be disabled by applying ground to the doff pin. for information refer to the application no te ?dll considerations in qdrii/ddrii/qdrii+/ddrii+?. note: 1. the above application shows four ddr-ii sio being used. application example [1] ld # r/w # b w # vt = v ref cc# cq cq# k# zq q d k cc# k bus master (cpu or asic) sram 1 sram 4 data in data out address ld# r/w# bws# sram 1 input cq sram 1 input cq# sram 4 input cq sram 4 input cq# source k source k# delayed k delayed k# r = 50 ohms r = 250 ohms cq cq# k# zq q ld # r/w # b w s # ld # r/w # vt vt vt r r r a a d r = 250 ohms b w s # [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 9 of 27 truth table [2, 3, 4, 5, 6, 7] operation k ld r/w dq dq write cycle: load address; wait one cycle; input write data on consecutive k and k rising edges. l-h l l d(a + 0) at k(t + 1) d(a + 1) at k (t + 1) read cycle: load address; wait one and a half cycle; read data on consecutive c and c rising edges. l-h l h q(a + 0) at c (t + 1) q(a + 1) at c(t + 2) nop: no operation l-h h x high-z high-z standby: clock stopped stopped x x previous state previous state write cycle descriptions (cy7c1392bv18 and cy7c1393bv18) [2, 8] bws 0 /nws 0 bws 1 /nws 1 kk comments l l l-h - during the data portion of a write sequence : cy7c1392bv18 ? both nibbles (d [7:0] ) are written into the device, cy7c1393bv18 ? both bytes (d [17:0] ) are written into the device. l l - l-h during the data portion of a write sequence : cy7c1392bv18 ? both nibbles (d [7:0] ) are written into the device, cy7c1393bv18 ? both bytes (d [17:0] ) are written into the device. l h l-h - during the data portion of a write sequence : cy7c1392bv18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1393bv18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. l h - l-h during the data portion of a write sequence : cy7c1392bv18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1393bv18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. h l l-h ? during the data portion of a write sequence : cy7c1392bv18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1393bv18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h l ? l-h during the data portion of a write sequence : cy7c1392bv18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1393bv18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h h l-h ? no data is written into the devices during this portion of a write operation. h h ? l-h no data is written into the devices during this portion of a write operation. notes: 2. x = ?don't care,? h = logic high, l = logic low, represents rising edge. 3. device will power-up deselected and the outputs in a tri-state condition. 4. ?a? represents address location latched by the devices when transaction was initiated. a + 0, a + 1 represents the internal a ddress sequence in the burst. 5. ?t? represents the cycle at which a read/write operation is started. t+1, t + 2 and t +3 are the first, second and third cloc k cycles succeeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c = high when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. assumes a write cycle was initiated per the write cycle description truth table. bws 0 , bws 1 in the case of cy7c1392bv18 and cy7c1393bv18 and also bws 2 , bws 3 in the case of cy7c1394bv18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 10 of 27 write cycle descriptions (cy7c1394bv18) [2, 8] bws 0 bws 1 bws 2 bws 3 kk comments l l l l l-h ? during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l l l l ? l-h during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l-h - during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. l h h h ? l-h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. h l h h l-h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h l h h ? l-h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h h l h l-h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h l h ? l-h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h h l l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. h h h l ? l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. hhhhl-h?no data is written into the device during this portion of a write operation. hhhh?l-hno data is written into the device during this portion of a write operation. write cycle descriptions (cy7c1992bv18) [2, 8] bws 0 kk comments l l-h ? during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. l ? l-h during the data portion of a write sequence, the single byte (d [8:0] ) is written into the device. h l-h ? no data is written into the device du ring this portion of a write operation. h ? l-h no data is written into the device du ring this portion of a write operation. [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 11 of 27 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-1900. the tap operates using jedec standard 1.8v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is ac tive depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v ss ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected betw een the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register s. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. seve ral no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr st ate. the idcode instruction [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 12 of 27 is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the in- struction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possi- ble that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sampl e/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system out put pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that t he tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the ?extest output bus tri-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bu s pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 13 of 27 note: 9. the 0/1 next to each state represents the value at tms at the rising edge of tck. tap controller state diagram [9] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 14 of 27 tap controller block diagram tap electrical characteristics over the operating range [10, 13, 14] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma 1.4 v v oh2 output high voltage i oh = ? 100 a1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 0.65v dd v dd + 0.3 v v il input low voltage ?0.3 0.35v dd v i x input and output load current gnd v i v dd ?5 5 a tap ac switching characteristics over the operating range [11, 12] parameter description min. max. unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 20 ns t tl tck clock low 20 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns notes: 10. these characteristics pertain to the tap inputs (tms, tck, td i and tdo). parallel load levels are specified in the electrica l characteristics table. 11. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 12. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. 13. overshoot: v ih (ac) < v dd +0.85v (pulse width less than t tcyc /2); undershoot v il (ac) > ?1.5v (pulse width less than t tcyc /2). 14. all voltage referenced to ground. 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 15 of 27 t cs capture set-up to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions [12] tap ac switching characteristics over the operating range (continued) [11, 12] parameter description min. max. unit (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9v 50 ? 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data-in tdi test data-out t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox tdo [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 16 of 27 identification register definitions instruction field value description cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010100010000101 11010100010001101 11010100010010101 11010100010100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 1 1 indicate the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input/output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/ou tput contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the inpu t/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and td o. this operation does not affect sram operation. [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 17 of 27 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 27 11h 54 7b 81 3g 1 6p 28 10g 55 6b 82 2g 26n 299g 566a 831j 3 7p 30 11f 57 5b 84 2j 4 7n 31 11g 58 5a 85 3k 57r 329f 594a 863j 6 8r 33 10f 60 5c 87 2k 7 8p 34 11e 61 4b 88 1k 8 9r 35 10e 62 3a 89 2l 9 11p 36 10d 63 1h 90 3l 10 10p 37 9e 64 1a 91 1m 11 10n 38 10c 65 2b 92 1l 12 9p 39 11d 66 3b 93 3n 13 10m 40 9c 67 1c 94 3m 14 11n 41 9d 68 1b 95 1n 15 9m 42 11b 69 3d 96 2m 16 9n 43 11c 70 3c 97 3p 17 11l 44 9b 71 1d 98 2n 18 11m 45 10b 72 2c 99 2p 19 9l 46 11a 73 3e 100 1p 20 10l 47 internal 74 2d 101 3r 21 11k 48 9a 75 2e 102 4r 22 10k 49 8b 76 1e 103 4p 23 9j 50 7c 77 2f 104 5p 24 9k 51 6c 78 3f 105 5n 25 10j 52 8a 79 1g 106 5r 26 11j 53 7a 80 1f [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 18 of 27 power-up sequence in ddr-ii sram [15, 16] ddr-ii srams must be powered up and initialized in a predefined manner to prevent undefined operations. power-up sequence ? apply power and drive doff low (all other inputs can be high or low) ?apply v dd before v ddq ?apply v ddq before v ref or at the same time as v ref ? after the power and clock (k, k , c, c ) are stable take doff high ? the additional 1024 cycles of clocks are required for the dll to lock dll constraints ? dll uses either k or c clock as its synchronizing input.the input should have low phase jitter, which is specified as t kc var ? the dll will function at frequencies down to 80 mhz ? if the input clock is unstable and the dll is enabled, then the dll may lock to an incorrect frequency, causing unstable sram behavior notes: 15. it is recommended that the doff pin be pulled high via a pull up resistor of 1kohm. 16. during power-up, when the doff is tied high, the dll gets locked after 1024 cycles of stable clock. power-up waveforms > 1024 stable clock start normal operation doff stabl e (< +/- 0.1v dc per 50ns ) fix high (or tied to v ddq ) k k ddq dd v v / ddq dd v v / clock start ( clock starts after stable ) ddq dd v v / ~ ~ ~ ~ unstable clock [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 19 of 27 maximum ratings (above which the useful life may be impaired.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with powe r applied .. ?55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +2.9v supply voltage on v ddq relative to gnd ...... ?0.5v to +v dd dc voltage applied to outputs in high-z state .................................... ?0.5v to v ddq + 0.3v dc input voltage [13] ............................ ?0.5v to v ddq + 0.3v current into outputs (low).... ..................................... 20 ma static discharge voltage (m il-std-883, m 3015)... > 2001v latch-up current.................................................... > 200 ma operating range range ambient temperature v dd [17] v ddq [17] com?l 0c to +70c 1.8 0.1v 1.4v to v dd ind?l ?40c to +85c electrical characteristics over the operating range [14] dc electrical ch aracteristics over the operating range parameter description test conditions min. typ. max. unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v oh output high voltage note 18 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 19 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ? 0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage [13] v ref + 0.1 v ddq + 0.3 v v il input low voltage [13] ?0.3 v ref ? 0.1 v i x input leakage current gnd v i v ddq ?5 5 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a v ref input reference voltage [20] typical value = 0.75v 0.68 0.75 0.95 v i dd v dd operating supply v dd = max.,i out = 0 ma, f = f max = 1/t cyc 167 mhz 450 ma 200 mhz 500 ma 250 mhz 550 ma 278 mhz 580 ma 300 mhz 600 ma i sb1 automatic power-down current max. v dd , both ports deselected, v in v ih or v in v il ,f = f max = 1/t cyc , inputs static 167 mhz 200 ma 200 mhz 220 ma 250 mhz 240 ma 278 mhz 250 ma 300 mhz 260 ma ac input requirements over the operating range parameter description test conditions min. typ. max. unit v ih input high voltage v ref + 0.2 ? ? v v il input low voltage ? ? v ref ? 0.2 v notes: 17. power-up: assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 18. outputs are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 19. outputs are impedance controlled. i ol =(v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 20. v ref (min.) = 0.68v or 0.46v ddq , whichever is larger, v ref (max.) = 0.95v or 0.54v ddq , whichever is smaller. [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 20 of 27 capacitance [21] parameter description test conditions 165 fbga package unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v v ddq = 1.5v 5pf c clk clock input capacitance 6 pf c o output capacitance 7pf thermal resistance [21] parameter description test conditions max. unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuri ng thermal impedance, per eia/jesd51. 28.51 c/w jc thermal resistance (junction to case) 5.91 c/w ac test loads and waveforms notes: 21. tested initially and after any design or process change that may affect these parameters. 22. unless otherwise noted, test conditions assume signal transit ion time of 2v/ns, timing reference levels of 0.75v, v ref = 0.75v, rq = 250 ? , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. 1.25v 0.25v r = 50 ? 5pf all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75v v ref = 0.75v [22] 0.75v under te s t 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ? [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 21 of 27 switching characteristics over the operating range [22,23] cypress parameter consortium parameter description 300 mhz 278 mhz 250 mhz 200 mhz 167 mhz unit min. max. min. max. min. max. min. max. min. max. t power v dd (typical) to the first access [24] 11111ms t cyc t khkh k clock and c clock cycle time 3.30 5.25 3.4 5.25 4.0 6.3 5.0 7.9 6.0 8.4 ns t kh t khkl input clock (k/k and c/c ) high 1.32 ? 1.4 ? 1.6 ? 2.0 ? 2.4 ? ns t kl t klkh input clock (k/k and c/c ) low 1.32 ? 1.4 ? 1.6 ? 2.0 ? 2.4 ? ns t khk h t khk h k clock rise to k clock rise and c to c rise (rising edge to rising edge) 1.49 ? 1.6 ? 1.8 ? 2.2 ? 2.7 ? ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 1.45 0.0 1.55 0.0 1.8 0.0 2.2 0.0 2.7 ns set-up times t sa t avkh address set-up to k clock rise 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns t sc t ivkh control set-up to k clock rise (ld , r/w ) 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns t scddr t ivkh double data rate control set-up to clock (k, k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.3 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns t sd [25] t dvkh d [x:0] set-up to clock (k/k ) rise 0.3 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns hold times t ha t khax address hold after k clock rise 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns t hc t khix control hold after k clock rise (ld , r/w ) 0.4 ? 0.4 ? 0.5 ? 0.6 ? 0.7 ? ns t hcddr t khix double data rate control hold after clock (k, k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.3 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.3 ? 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.50 ns t doh t chqx data output hold after output c/c clock rise (active to active) ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.50 ? ns t ccqo t chcqv c/c clock rise to echo clock valid ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.50 ns notes: 23. all devices can operate at clock frequencies as low as 119 mhz. when a part with a maximum frequency above 133 mhz is operat ing at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range. 24. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 25. for d2 data signal on cy7c1992bv18 device, t sd is 0.5 ns for 200 mhz, 250 mhz, 278 mhz and 300 mhz frequencies. [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 22 of 27 t cqoh t chcqx echo clock hold after c/c clock rise ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.50 ? ns t cqd t cqhqv echo clock high to data change ? 0.27 ? 0.27 ? 0.30 ? 0.35 ? 0.40 ns t cqdoh t cqhqx echo clock high to data change ?0.27 ? ?0.27 ? ?0.30 ? ?0.35 ? ?0.40 ? ns t chz t chqz clock (c/c ) rise to high-z (active to high-z) [26, 27] ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.50 ns t clz t chqx1 clock (c/c ) rise to low-z [26, 27] ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.50 ? ns dll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ? 0.20 ? 0.20 ? 0.20 ns t kc lock t kc lock dll lock time (k, c) 1024 ? 1024 ? 1024 ? 1024 ? 1024 ? cycles t kc reset t kc reset k static to dll reset 30 30 30 30 30 ns notes: 26. t chz , t clz , are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 100 mv from steady-state voltage. 27. at any given voltage and temperature t chz is less than t clz and t chz less than t co . switching characteristics over the operating range [22,23] (continued) cypress parameter consortium parameter description 300 mhz 278 mhz 250 mhz 200 mhz 167 mhz unit min. max. min. max. min. max. min. max. min. max. [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 23 of 27 switching waveforms [28, 29, 30] notes: 28. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, i.e., a0 + 1. 29. output are disabled (high-z) one clock cycle after a nop. 30. in this example, if address a2 = a1,then data q20 = d10 and q21 = d11. write data is forwarded immediately as read results. this note applies to the whole diagram k 1234567 8 k ld r/w a q d c c# read (burst of 2) read (burst of 2) read (burst of 2) write (burst of 2) write (burst of 2) t khch t khch nop nop cq cq# t kh t khkh t co t kl t cyc t t hc t sa t ha t sd t hd t sd t hd t clz t doh sc t kh t khkh t kl t cyc t cqd t ccqo t cqoh t ccqo t cqoh dont care undefined a0 a1 a2 a3 a4 d20 d21 d30 d31 q40 q11 q10 q41 q00 q01 t cqdoh t chz [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 24 of 27 ordering information not all of the speed, package and temperature ranges are avai lable. please contact your lo cal sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range 167 cy7c1392bv18-167bzc 51-85180 1 65-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1992bv18-167bzc cy7c1393bv18-167bzc cy7c1394bv18-167bzc cy7c1392bv18-167bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-167bzxc cy7c1393bv18-167bzxc cy7c1394bv18-167bzxc cy7c1392bv18-167bzi 51-85180 165- ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1992bv18-167bzi cy7c1393bv18-167bzi cy7c1394bv18-167bzi cy7c1392bv18-167bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-167bzxi cy7c1393bv18-167bzxi cy7c1394bv18-167bzxi 200 cy7c1392bv18-200bzc 51-85180 1 65-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1992bv18-200bzc cy7c1393bv18-200bzc cy7c1394bv18-200bzc cy7c1392bv18-200bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-200bzxc cy7c1393bv18-200bzxc cy7c1394bv18-200bzxc cy7c1392bv18-200bzi 51-85180 165- ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1992bv18-200bzi cy7c1393bv18-200bzi cy7c1394bv18-200bzi cy7c1392bv18-200bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-200bzxi cy7c1393bv18-200bzxi cy7c1394bv18-200bzxi 250 cy7c1392bv18-250bzc 51-85180 1 65-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1992bv18-250bzc cy7c1393bv18-250bzc cy7c1394bv18-250bzc cy7c1392bv18-250bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-250bzxc cy7c1393bv18-250bzxc cy7c1394bv18-250bzxc [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 25 of 27 250 cy7c1392bv18-250bzi 51-85180 1 65-ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1992bv18-250bzi cy7c1393bv18-250bzi cy7c1394bv18-250bzi cy7c1392bv18-250bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-250bzxi cy7c1393bv18-250bzxi cy7c1394bv18-250bzxi 278 cy7c1392bv18-278bzc 51-85180 1 65-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1992bv18-278bzc cy7c1393bv18-278bzc cy7c1394bv18-278bzc CY7C1392BV18-278BZXC 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-278bzxc cy7c1393bv18-278bzxc cy7c1394bv18-278bzxc cy7c1392bv18-278bzi 51-85180 165- ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1992bv18-278bzi cy7c1393bv18-278bzi cy7c1394bv18-278bzi cy7c1392bv18-278bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-278bzxi cy7c1393bv18-278bzxi cy7c1394bv18-278bzxi 300 cy7c1392bv18-300bzc 51-85180 1 65-ball fine pitch ball grid array (13 x 15 x 1.4 mm) commercial cy7c1992bv18-300bzc cy7c1393bv18-300bzc cy7c1394bv18-300bzc cy7c1392bv18-300bzxc 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-300bzxc cy7c1393bv18-300bzxc cy7c1394bv18-300bzxc cy7c1392bv18-300bzi 51-85180 165- ball fine pitch ball grid array (13 x 15 x 1.4 mm) industrial cy7c1992bv18-300bzi cy7c1393bv18-300bzi cy7c1394bv18-300bzi cy7c1392bv18-300bzxi 51-85180 165-ball fine pitch ball grid array (13 x 15 x 1.4 mm) lead-free cy7c1992bv18-300bzxi cy7c1393bv18-300bzxi cy7c1394bv18-300bzxi ordering information (continued) not all of the speed, package and temperature ranges are avai lable. please contact your lo cal sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 26 of 27 qdr ? srams and quad data rate ? srams comprise a new family of products developed by cypress, hitachi, idt, micron, nec and samsung technology. all product and company names mentio ned in this document are the trademarks of their respective holders. package diagram a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25mcab ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin1corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 -0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a 165 fbga 13 x 15 x 1.40 mm bb165d/bw165d a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 - 0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a 165-ball fbga (13 x 15 x 1.4 mm) (51-85180) [+] feedback [+] feedback
cy7c1392bv18 cy7c1992bv18 cy7c1393bv18 cy7c1394bv18 document number: 38-05623 rev. *c page 27 of 27 document history page document title: cy7c1392bv18/cy7c 1992bv18/cy7c1393bv18/cy7c1394bv18 18-mbit ddr-ii sio sram 2-word burst architecture document number: 38-05623 rev. ecn no. issue date orig. of change description of change ** 252474 see ecn syt new data sheet *a 325581 see ecn syt removed cy7c1992bv18 from the title included 300-mhz speed bin added industrial temperature grade replaced tbds for i dd and i sb1 specs replaced the tbds on the thermal characteristics table to ja = 28.51 c/w and jc = 5.91 c/w replaced tbds in the capacitance table for the 165 fbga package changed the package diagram from bb165e (15 x 17 x 1.4 mm) to bb165d (13 x 15 x 1.4 mm) added lead-free product information updated the ordering information by shading and unshading mpns as per availability *b 413997 see ecn nxr converted from preliminary to final added cy7c1992bv18 part number to the title added 278-mhz speed bin changed address of cypress semicondu ctor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed c/c pin description in the features section and pin description added power-up sequence details and waveforms added foot notes #15, 16, 17 on page# 18 replaced three-state with tri-state changed the description of i x from input load current to input leakage current on page# 19 modified the i dd and i sb values modified test condition in footnote #18 on page# 19 from v ddq < v dd to v ddq < v dd replaced package name column with package diagram in the ordering information table updated the ordering information *c 472384 see ecn nxr modified the zq definition from alternately, this pin can be connected directly to v dd to alternately, this pin can be connected directly to v ddq included maximum ratings for supply voltage on v ddq relative to gnd changed the maximum ratings for dc input voltage from v ddq to v dd changed t th and t tl from 40 ns to 20 ns, changed t tmss , t tdis , t cs , t tmsh , t tdih , t ch from 10 ns to 5 ns and changed t tdov from 20 ns to 10 ns in tap ac switching characteristics table modified power-up waveform changed the maximum rating of ambient temperature with power applied from ?10c to +85c to ?55c to +125c added additional notes in the ac parameter section modified ac switching waveform corrected the typo in the ac s witching characteristics table updated the ordering information table [+] feedback [+] feedback

▲Up To Search▲

Price & Availability of CY7C1392BV18-278BZXC

	To Download CY7C1392BV18-278BZXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .